250 MHz Multiphase Delay Locked Loop for Low Power Applications
نویسندگان
چکیده
Received Mar 17, 2017 Revised Sep 8, 2017 Accepted Sep 20, 2017 Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18umCMOS technology and at power supply of 1.8V . It has power consumption of 1.39 mW at 125 MHzcenter frequency with locking range from 0.5 MHzto 250 MHz. Keyword:
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